EE410
 
Northwestern Polytechnic University
Course Syllabus
MODERN EDA TOOLS (EE410)
 2007 Summer (05/02/2007 updated)
Course Description
  This course is designed to introduce Electrical Engineering and Computer System Engineering students to a wide variety of industry standard CAD and EDA software for microelectronic circuits and system design at both board and chip level. Many of these tools are used in higher level EE courses. The course starts with a review of PC and UNIX basics including commands, directory structuring, executable batch file creation, and automation script programming such as PERL, etc., followed by an introduction to popular CAD/EDA tools used by high-tech industry. The management and the design methodology of a subset of these tools will be described. The students receive an introduction to design tools available on campus and their usage at various levels of courses in circuit design, logic design implementation, physical design, performance analysis, and design verification.
 
Prerequisites
  Senior standing or instructor consent.
 
Instructor Information
  Name: Ms. Anna Wei
Email: annawei2@yahoo.com
 
Instruction Methods
  Lectures, lab works, in class discussions, homeworks, projects.
 
Teaching Strategies
  Knowledge repetition and reinforcement; hands-on lab works; emphasis on problem solving skills; coding practice.
 
Course Information
  units: 3 units/15 weeks

Hours:

 3 hour lecture/week
  Time: Saturdays, 9:30 A.M. - 12:20 P.M.
 
Textbook Information
  Title: Instructor's Notes
Author: N/A
ISBN: N/A
publisher: N/A
Notes: Students are not allowed to use previous edition textbook.
 
Reference book Information
  Title: UNIX MADE EASY, 3rd Edition, By John Muster
ISBN: 007219314x Publisher: McGraw Hill, 2003
 
Course Objectives
Students will gain knowledge and skills of interaged circuit design methodologies using modern EDA tools. Students will become familiar with the design flow from schematic capture, simulation, to physical implementation and verification using CAD tools available on the campus.
 
Grading Policy
Lecture percentage: 100 % 
Homework Midterm Final Project Presentation Participation Quizzes Others
30% 20% 0% 20% 20% 10% 0% 0%
 
Weekly Activities:
1 Objectives: During this first class meeting, the instructor and students will get acquaintant with each other. Then, the instructor will introduce the EDA tools in the industry wide application and emphasize on the CAD tools available on the NPU campus for the integrated circuit designs.
Instructive Coverage & Activities: The instructor will introduce the course with administrative details, grading policy, assignments, and discuss the topics in the syllabus. Students will be asked to talk about their expectations and special needs from the course.
Assignments: Please read the Handouts on "Introduction to Modern EDA Tools".
2 Objectives: At this class meeting, the instructor will introduce the basics of Unix operating systems. Students will have a hands-on review of Unix basics.
Instructive Coverage & Activities: We will review the UNIX basics including the basic commands, directory structuring, file editor, file security, environment variables, system printing, remote connections, interactive communications. Students will do the command exercises following the handouts.
Assignments: Please read the handouts on "Introduction to UNIX" and do the command exercises in the handouts.
3 Objectives: At this class meeting, the instructor will introduce the Cadence Design Framework II. The students will gain an overview of knowledge on Cadence Design Framework II and learn how to invoke the Cadence Design Framework II at the campus environments.
Instructive Coverage & Activities: This lecture will cover the following topics:
1. An overview of Cadence Design Framework II.
2. Starting the Design Framework II with initialization files.
3. Features of the Design Framework II.
4. Openbook online documentation.
The students will invoke the tool and go through the tool features.
Assignments: Please read the handouts on "Introduction to Cadence Design Framework II", and invoke the DF II and OPENBOOK.
4 Objectives: At this class meeting, we will discuss the database and library structure within Cadence Design Framework II. The students will learn how the design databases are managed by Library Manager tool.
Instructive Coverage & Activities: We will discuss the Library Manager tool, which is embedded within Cadence Design Framework II, and cover the followng topics:
1. Design batabase structure.
2. Dasign batabase version control.
3. Library definitions in cds.lib file.
Students will invoke the tool and learn how the Library Manager tool works for the design database management.
Assignments: Please read the handouts on "Cadence Design Framework II - Library Manager" and invoke the Library Manager tool.
5 Objectives: At this class meeting, the instrutor will present Cadence Schematic Composer tool. The students will learn the hands-on skills as to how draw a schematic with the given parameters.
Instructive Coverage & Activities: We will cover the following topics:
1. Brief review of circuit design concepts.
2. Schematic capture using Composer.
3. Creating instances, wires, pins.
4. Connecting all components.
5. Creating schematic symbols.
6. Generating a netlist from netlist from the schematic. The students will draw an inverter schematic and generate a netlist in class.
Assignments: Please read the handouts on "Cadence Schematic Composer" and invoke the tool to do the homework assignments.
Quiz/Test/Exam: The homework-1 will be posted on LRC and due next week.
6 Objectives: At this class meeting, the instructor will introduce AVANT! HSPICE simulation tool. The students will learn how to simulate a circuit netlist with HSPICE.
Instructive Coverage & Activities: This lecture will cover the following topics:
1. HSPICE simulation concept and flow.
2. Circuit netlist generation.
3. Running the simulation.
4. Invoking AWAVE to display the simulation results.
The students will run HSPICE simulation with an inverter netlist and invoke the AWAVE tool to see the waveform.
Assignments: Please read the handouts on "Introduction to HSPICE Circuit Simulation", and run HSPICE for the homework assignment.
Quiz/Test/Exam: 1. The instructor will collect the homework-1 in the beginning of the class and grade the homeworks after class.
2. The homework-2 will be posted on LRC and due next week.
7 Objectives: This week will be midterm. The midterm will contain six questions, each of which will be derived from each week's lecture notes from week-1 to week-6. First question will come from the CAD tool usages. Second question will ask for the Unix commands. Third question will come from Cadence Design Framework II. Fourth question will cover Library Manager tool. Fifth question will come from the schematic composer tool. Sixth question will cover HSPICE simulation tool.
Instructive Coverage & Activities: First, the instructor will go through the problems and solutions for homework-1 and homework-2. Then, the students will be given the midterm questions. Students need to answer questions in writing on a 90 minute basis.
Assignments: The instructor will collect the homework-2 in the begining of the class and grade the homeworks after class.
8 Objectives: At this class meeting, the instructor will introduce the Cadence Virtuoso tool for the custom layout. The integrated circuit fabrication process and design rule will be discussed. The students will learn the methodologies of custom layout using Virtuoso.
Instructive Coverage & Activities: This week lecture will cover the following topics:
1. Custom layout design using Virtuoso tool.
2. Integrated circuit fabrication process.
The students will view the demo of the custom layout design.
Assignments: Please read the handouts on "Introduction to Cadence Virtuoso for Custom Layout Design" Part I.
9 Objectives: At this class meeting, we will continue on Virtuoso Layout Design and discuss the design technology. The students will learn how to interpret a schematic to a layout and draft the transistor devices.
Instructive Coverage & Activities: This week lecture will cover the following topics:
1. Virtuso Layer Select Window Vs Design Technology File.
2. Drafting the transistor devices.
3. Drafting the interconnections and pins.
The students will draft an inverter layout based on the 0.18um tsmc technology.
Assignments: Please read the handouts on "Introduction to Cadence Virtuoso For Custom Layout Design" Part II.
10 Objectives: At this class meeting, we will continue the Virtuoso layout design and discuss the foundry design rules. Students will finish a full custom layout with design rule checking.
Instructive Coverage & Activities: This lecture will cover the followings:
1. Foundry design rules.
2. DIVA online design rule check.
Assignments: 1. Please read the handouts on "Introduction to Cadence Virtuoso for Custom Layout Design" Part III.
2. Final project guideline will be posted on LRC for students to prepare their final projects.
Quiz/Test/Exam: The homework-3 will be posted on LRC and due next week.
11 Objectives: At this class meeting, the instructor will introduce the Mentor Graphic Calibre verification toolset. The Design Rule Check methodology will be presented. The students will learn how to run DRC on a given layout design by Calibre DRC tool.
Instructive Coverage & Activities: This lecture will cover the following topics:
1. Mentor Graphic Calibre verification toolset.
2. Design Rule Check flow.
3. Generating DRC rule file.
4. Running DRC on graphic user interface mode.
5. Examine and interpret the results.
The students will invoke the Calibre tool and run DRC on a custom layout design and interpret the error messages on the results. Then, students will correct the DRC errors on the layout and run DRC again until getting the zero error results.
Assignments: Please read the handouts on "Introduction to Mentor Graphic Calibre Design Rule Check" and do the lab works on DRC run.
Quiz/Test/Exam: The instructor will collect the homework-3 in the beginng of the class and grade the homeworks after the class.
12 Objectives: At this class meeting, we will continue on Calibre verfication toolset and discuss Layout Versus Schematic check. The students will learn how to run LVS on a given layout and netlist.
Instructive Coverage & Activities: This week lecture will cover the following topics:
1. Calibre Layout Versus Schematic flow.
2. Generating LVS rule file.
3. Running LVS on graphic user interface mode.
4. Examine the results.
The students will invoke the Calibre tool and run LVS on a given layout design and examine the error messages on the results. Then students will modify the layout based on the last run results, run LVS again until the layout design will be clean.
Assignments: Please read the handouts on "Introduction to Mentor Graphic Calibre Layout Versus Schematic" and do the lab works on LVS run.
Quiz/Test/Exam: The homework-4 will be posted on LRC and due next week.
13 Objectives: At this week meeting, we will discuss xCalibre Parasitic Extraction methodology. The students will learn how to run parasitic extraction on a given layout design.
Instructive Coverage & Activities: This week lecture will cover the following topics:
1. xCalibre Parasitic Extraction Flow.
2. Generating parasitic extraction rule file.
3. Running parasitic extraction on graphic user interface mode.
4. Examine the spice netlist with parasitic resistance and capacitance values.
The students will invoke the xCalibre tool and run PEX on a given layout design, and examine the spice netlist.
Assignments: Please read the handouts on "Introduction to Mentor Graphic Calibre Parasitic Extraction" and do the lab works on PEX run.
Quiz/Test/Exam: 1. The instructor will collect the homework-4 in the beginning of the class and grade the homeworks after the class.
2. The sulotions for homework-3 and homework-4 will be reviewed.
14 Objectives: This week will be the final project. The goal of final project is to train the students with the skills and capabilities to accomplish a design task using the CAD tools available in the campus.
Instructive Coverage & Activities: The final project may contain various aspects of CAD tool methodologies covered from week-1 to week-13 based on students' expertise and interest. The student will present their final projects using presentation slides with corresponding lab works. The students will be devided into two groups. At this week meeting, the first group of students will do the presentations. The instructor will collect the final project paperworks.
Assignments: Prepare for the Fianl Project Presentation.
15 Objectives: This week will be the final project. The students will be trained with the skills and abilities to accomplish a design task using CAD tools available in the campus.
Instructive Coverage & Activities: The final project may contain various aspects of CAD tool methodologies covered from week-1 to week-13 based on students' expertise and interests. The students will present their final projects using presentation slides with corresponding lab works. At this week meeting, the second group of students will do the presentations. The instructor will collect the final project paperworks.
Assignments: Final Project Presentation.
Reference Links
  http://www.mentor.com
  http://www.cadence.com/
 
Academic Integrity
  Any student who submits plagiarized work (another person's) shall receive a zero or or "F" on that homework, project or exam. Any student caught cheating on an exam shall receive an "F" in the entire course.
 
Attendance
  Students must attend all class meetings, with the exception of an emergency or illness. Students  who miss 4 or more class meetings for any reason will receive an "F" in the course.
 
Assignments
  Assignments are due on the date assigned by the instructor.
 
Makeup
  Late assignments, missed midterms and quizzes, etc. may be made up only with advance approval from the instructor.
 
Use of Library Resources in Assignments
  Students will use the Library Resources at NPU as well as the Internet to research information for assignments. You may also use San Jose State's Library. The NPU Library has a SJ State Library card. Specific assignments may require students to review technical journals, magazines, textbooks, and reference books located in the NPU Library.
 
Guidance and Direction to the Students
  The instructor and LA/TA (if applicable) are available to assist the students with the class materials and assignments.
 
Resources
  Journal articles, reprints from reference publications, audio-visual, handouts, and other technical material developed by the instructor will be used to supplement the textbooks.
 
Notes
  N/A
 
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