EE461
 
Northwestern Polytechnic University
Course Syllabus
VERILOG HDL & DIGITAL DESIGN (EE461)
2007 Summer (05/02/2007 updated)
Course Description
  This is the first of a series - EE461, EE510, EE512 - designed for the students to utilize industry grade design tools to design modern digital systems. This course develops the students' ability to design the basic building blocks of modern digital systems and provides them with a fundamental knowledge of the state-of-the-art design methodology, design considerations, and verification strategies for complicated digital hardware design. Topics include Verilog HDL basics, simulation, synthesis of digital systems using Verilog HDL. The students practice using the tools for design projects on UNIX system or Windows system. Mentor Modelsim for HDL Simulation, Cadence Verilog-XL, and Silo III Verilog Simulator from SimuCAD are available in the Labs. Hands-on practices are required.
 
Prerequisites
  EE323.
 
Instructor Information
  Name: Mr. Yingli Ren
Email: ren_yingli@yahoo.com
 
Instruction Methods
  Lecture material will be available at the NPU internal website during the second week of the course. Students are responsible for copying/printing the lecture notes. Lecture notes are organized as a collection of Microsoft word files and Microsoft power point files. Each class is divided into two parts: 2 hours lecture and 1 hour hands-on exercises using the computers. Students are encouraged to study the material before each class using both lecture notes and the textbook. Reading assignments are given in the lecture notes.
 
Teaching Strategies
  Knowledge reinforcement; coding practice.
 
Course Information
  units: 3 units/15 weeks

Hours:

 3 hour lecture/week
  Time: Saturdays, 1:30 P.M - 4:20 P.M
 
Textbook Information
  Title: Instructor's notes
Author: N/A
ISBN: N/A
publisher: N/A
Notes: Students are not allowed to use previous edition textbook.
 
Reference book Information
  Title: VERILOG Digital System Design by Zainalabedin Navabi
ISBN: 0070471649, Publisher: McGraw-Hill, 1999
  Title: Verilog HDL by Samir Palnitakar, 2nd edition
ISBN: 0130449113, Publisher: Prentice Hall PTR, 2003
 
Course Objectives
This course is designed to give students an opportunity to learn Verilog HDL language and its applications in the electronic industry. The focus of this course is logic modeling and simulation. Verilog HDL for synthesis is covered in both EE510 (Logic Synthesis) and EE512 (ASIC Design).
 
Grading Policy
Lecture percentage: 100 % 
Homework Midterm Final Project Presentation Participation Quizzes Others
20% 30% 30% 0% 0% 10% 10% 0%
 
Weekly Activities:
1 Objectives: Introduction:
1. Course Overview and Objectives.
2. Introduction to HDL.
3. HDL & Programming Language Comparison.
4. Brief Tutorial on Verilog-XL & other Verilog Simulators.
Instructive Coverage & Activities: Introduction to Verilog HDL, Software download, NPU CAD tools environment. Overview of roles Verilog HDL plays in hardware design in general.
Assignments: 1. Download free Verilog software from EDA tools vendor website.
2. Browse course material.
2 Objectives: Basic Concepts:
1. Lexical Conventions and Data Types.
2. Expressions and Assignments.
Instructive Coverage & Activities: Covering Verilog basic concepts: syntax & semantics.
Assignments: HW#1: Simulating a simple Verilog model using a Verilog Simulator.
3 Objectives: Logic Modeling I1. Switch & Gate Level Modeling 2. User-Defined Primitives (UDPs).
Instructive Coverage & Activities: Switch level modeling.
Assignments: HW#2: Work on Verilog operators and their precedence.
4 Objectives: Logic Modeling II:
1. always & initial blocks.
2. Tasks & Functions 3. Behavior Modeling.
Instructive Coverage & Activities: 1. Procedural blocks.
2. tasks & functions.
3. Behavior modeling.
Assignments: HW#3: Verilog gate level modeling exercise.
5 Objectives: Timing & Delay:
1. Basic timing concepts.
2. Delay Calculation.
3. Standard Delay Format (SDF).
4. Specify Blocks.
Instructive Coverage & Activities: 1. Basic timing concepts.
2. delay calculation.
3. SDF format.
Assignments: HW#4: Create User Defined Primitives (UDP) for combinational and sequential logic elements.
Quiz/Test/Exam: Quiz #1 on Verilog Basic concepts.
6 Objectives: Simulation I:
1. Hierarchical structures.
2. Using External libraries.
3. Timescale & Delay scaling.
Instructive Coverage & Activities: 1. Hierarchical structures.
2. Using External libraries.
3. Time scale & time scaling.
Assignments: HW#5: Behavior level modeling style exercise.
7 Objectives: Simulation II:
1. Timing Checks.
2. Delay Annotation.
Instructive Coverage & Activities: 1. Timing checks.
2. Delay annotation.
Assignments: Review & Reading.
8 Objectives: Summary for topics so far & Midterm Exam.
Instructive Coverage & Activities: 1. Review, question & answer.
2. Midterm exam.
Assignments: HW#6: Modeling behavior using different levels of abstraction.
9 Objectives: Synthesis using Verilog HDL:
1. Synthesis Overview.
2. Combinational Logic.
3. Sequential Logic.
4. Synthesis examples.
Instructive Coverage & Activities: 1. Synthesis overview.
2. supported Verilog construct.
Assignments: HW#7: Modeling a complex binary counter.
10 Objectives: Writing Verilog test fixture.
Instructive Coverage & Activities: 1. Overview.
2. Different fixture styles.
3. Simulating sequential circuits.
4. Simulating bidirectional ports.
Assignments: HW#8: Hierarchical modeling styles.
11 Objectives: Memory Modeling:
1. RAM and ROM models.
2. Simple FIFO models.
Instructive Coverage & Activities: 1. Memory types & terminologies.
2. parameterized memory modeling.
3. FIFO modeling.
Assignments: HW#9: Modeling state machine using Verilog HDL.
Quiz/Test/Exam: Quiz #2 On Verilog behavior modeling.
12 Objectives: Modeling a complex Digital system Using Verilog HDL:
1. Modeling a complex system using top-down approach.
2. Converting specifications into Verilog models.
Instructive Coverage & Activities: 1. Top down design method.
2. Converting a specification into Verilog HDL description.
Assignments: HW#10: Memory modeling.
13 Objectives: Issues and techniques in logic modeling using Verilog HDL.
Instructive Coverage & Activities: 1. Clarification on Verilog HDL.
2. Sample usages.
Assignments: Additional Reading from instructor.
14 Objectives: Finite State Machine Related Topics:
1. State Minimization.
2. Modeling State Machines using Verilog HDL.
Instructive Coverage & Activities: 1. State machine review.
2. State minimization.
3. State machine design using Verilog HDL.
Assignments: Course review & prepare for final.
15 Objectives: Further study in this area & Final Exam.
Instructive Coverage & Activities: 1. Further study in Verilog HDL & related courses.
2. Final Exam.
Assignments: Last day to turn in course work.
Reference Links
  http://www.verilog.com/
  http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html
 
Academic Integrity
  Any student who submits plagiarized work (another person's) shall receive a zero or or "F" on that homework, project or exam. Any student caught cheating on an exam shall receive an "F" in the entire course.
 
Attendance
  Students must attend all class meetings, with the exception of an emergency or illness. Students  who miss 4 or more class meetings for any reason will receive an "F" in the course.
 
Assignments
  Assignments are due on the date assigned by the instructor.
 
Makeup
  Late assignments, missed midterms and quizzes, etc. may be made up only with advance approval from the instructor.
 
Use of Library Resources in Assignments
  Students will use the Library Resources at NPU as well as the Internet to research information for assignments. You may also use San Jose State's Library. The NPU Library has a SJ State Library card. Specific assignments may require students to review technical journals, magazines, textbooks, and reference books located in the NPU Library.
 
Guidance and Direction to the Students
  The instructor and LA/TA (if applicable) are available to assist the students with the class materials and assignments.
 
Resources
  Journal articles, reprints from reference publications, audio-visual, handouts, and other technical material developed by the instructor will be used to supplement the textbooks.
 
Notes
  N/A
 
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