EE506
Northwestern Polytechnic University
Course Syllabus
Advanced digital IC Design
(EE506)
2007 Summer (05/02/2007 updated)
Course Description
This course is a continuation of the course EE505 and is designed to cultivate students’ ability to design a Standard Cell Library, Datapath and other special circuits that can be used as intellectual properties (IP) building blocks for ASIC, SOC (system on chip) and DSP (digital signal processing) applications. In addition to the design subject, student also learn how to generate different views of the circuits to facilitate system integration with various CAD tools for logic synthesis and physical implementations. Topics include standard cell design and characterization, technology mapping, design rules, layout, datapath synthesis, memory compiler, IP development and architecture trade-off. Modern CAD tools such as Synopsys, OPUS, Composer, Virtuoso, HSPICE and Mentor’s Calibre will be introduced and used for homework assignment and projects.
Prerequisites
EE505.
Instructor Information
Name:
Mr. H Su
Email:
huayusu@yahoo.com
Instruction Methods
Lecture, discussions, in-class exercises, design project, and tests.
Teaching Strategies
Knowledge repetition and reinforcement, hand-on design skill.
Course Information
units:
3 units/15 weeks
Hours:
3 hour lecture/week
Time:
Wednesdays, 6:50 P.M. - 9:40 P.M.
Textbook Information
Title:
Digital Integrated Circuits, 2nd edition
Author:
Jan M. Rabaey
ISBN:
0130909963
publisher:
Prentice Hall, 2001
Notes:
Students are
not
allowed to use previous edition textbook.
Reference book Information
Title:
CMOS Logic Circuit Design by John P. Uyemura
ISBN:
0-7923-8452-0, Published by Kluwer Academic Publis
Title:
Digital Systems Engineering, by William and John
ISBN:
0-521-59292-5, Published by Cambridge University P
Title:
Circuits, Interconnections and Packaging for VLSI, By H. Bakoglu
ISBN:
0201060086, Published by Addison-Wesley Pub Co, 19
Course Objectives
1. Understand VLSI from circuit perspective and system perspective.
2. Understand cell-based and IP and their role in IC design.
3. Understand datapath and memory core, their architecture, realization and applications.
Grading Policy
Lecture percentage: 100 %
Homework
Midterm
Final
Project
Presentation
Participation
Quizzes
Others
20%
20%
20%
20%
0%
0%
20%
0%
Weekly Activities:
1
Objectives:
* Course Syllabus and grading policy.
* CAD tool.
* VLSI key points review.
Instructive Coverage & Activities:
(1) Review key points of VLSI design (Circuit & Layout).
(2) Introduce more HSPICE features for circuit simulation.
(3) Introduce tools: circuit simulator, logic simulator, layout verification tool, RC extraction tool.
Assignments:
* Review Handout.
* Homework.
Others:
* In-class exercise: run HSPICE.
* Exercise some useful features in HSPICE.
2
Objectives:
* Device model for different process corners.
* Single leaf cell layout design and DRC/LVS.
Instructive Coverage & Activities:
(1) Lecture on device model for the corners of SS, FF, TT, SF & FS.
(2) Lecture on how to layout a leaf cell.
(3) Present layout verification: DRC/LVS.
Assignments:
* Review Handout.
* Homework.
Others:
In-class exercise: Simulation at corners.
3
Objectives:
* Learn about building a subcircuit.
* Learn about sequential logic circuit design (1).
Instructive Coverage & Activities:
Lecture on static latch and register such as multiplexer base latch, master-slave edge-triggered register ...
Assignments:
* Review handout and 7.1, 7.2.
* Homework.
Others:
Build the subcircuit for basic logic gates.
4
Objectives:
Learn about sequential logic circuits (2).
Instructive Coverage & Activities:
(1) Lecture on dynamic latches and registers such as dynamic transmission gate edge-triggered register, C^2MOS and TSPCR.
(2) Lecture on Pulse register and Sense-amplifier based register.
Assignments:
* Review handout and 7.3, 7.4.
* Homework.
Others:
Review key points for next week's midterm (1).
5
Objectives:
* Learn about Pipelining.
* Learn about nonbistable sequential logic circuits Midterm(1).
Instructive Coverage & Activities:
(1) Lecture on the concept of pipelining.
(2) Lecture on Schmitt trigger, monostable circuits and astable circuits.
Assignments:
* Review handout and 7.5, 7.6.
* Homework.
Quiz/Test/Exam:
Midterm (1)(60 minutes).
6
Objectives:
* Review Midterm (1).
* Learn about custom circuit design --- cell-based design methodology.
Instructive Coverage & Activities:
(1) Lecture on a typical design flow for custom circuit design.
(2) Lecture on cell-based design approach: standard cell, compiled cell and IP.
Assignments:
* Review handout and 8.1, 8.2, 8.3 and 8.4.
* Homework.
Others:
Review Midterm (1) and discuss the solutions.
7
Objectives:
* Learn about custom circuit design --- array-based design methodology.
* Learn about coping with interconnect.
Instructive Coverage & Activities:
(1) Lecture on array-based implementation approaches such as programmable array and prewired array.
(2) Lecture on capacitive parasitics.
Assignments:
* Review handout and 8.5, 9.2.
* Homework.
8
Objectives:
Learn about coping with interconnect.
Instructive Coverage & Activities:
(1) Lecture on resistive parasitics --- ohmic voltage drop, electromigration, RC delay.
(2) Lecture on inductive parasitics --- voltage drop, transmission line effect.
Assignments:
* Review handout and 9.3, 9.4.
* Homework.
9
Objectives:
* How to design I/O buffer and output driver.
* How to layout I/O.
Instructive Coverage & Activities:
(1) Lecture on I/O buffer design (size, circuits, noise, loading).
(2) Lecture on I/O layout.
Assignments:
* Review handout and 9.4, 9.5.
* Homework.
Others:
Review the key points for next week's midterm (2).
10
Objectives:
* Discuss design project.
* Midterm (2).
* Learn about timing issues in digital circuits.
Instructive Coverage & Activities:
Lecture on synchronous design --- clock distribution techniques, clock skew and jitter.
Assignments:
* Review handout and 10.1, 10.2, 10.3.
* Homework.
Quiz/Test/Exam:
* Midterm (2)(60 minutes).
* Assign design projects.
11
Objectives:
* Review Midterm (2).
* Learn about self-timed circuits design.
* Learn about PLL and DLL.
Instructive Coverage & Activities:
(1) Lecture on self-timed logic and post-charge logic.
(2) Lecture on PLL --- VCO, phase dector, charge-pump.
(3) Lecture on Delay Locked Loop.
Assignments:
* Review handout and 10.4, 10.5, 10.6, 10.7.
* Homework.
12
Objectives:
Learn about adder and multiplier.
Instructive Coverage & Activities:
(1) Lecture on binary adder (logic design consideration): carry-bypass adder, square-root carry-select adder...
(2) Lecture on multiplier.
Assignments:
* Review handout and 11.2, 11.3, 11.4.
* Homework.
13
Objectives:
* Learn about power and speed trade-off in data path.
* Learn about memory core.
Instructive Coverage & Activities:
(1) Lecture on power reduction techniques --- design for low power.
(2) Lecture on ROM, NVM, RAM and CAM.
Assignments:
* Review handout and 11.7, 12.1, 12.2.
* Homework.
14
Objectives:
Learn about memory peripheral circuitry.
Instructive Coverage & Activities:
(1) Lecture on address decoder, sense amplifier, buffers.
(2) Lecture on architecture design and memory chip plan.
(3) Present a simple SRAM design as an example.
Assignments:
* Review handout and 12.3.
* Homework.
Others:
* In-class exercise: how to build a critical path for simulation.
* Review the key points for next week's final exam.
15
Objectives:
* General review.
* Final exam.
Instructive Coverage & Activities:
Overall review the key points on VLSI (IP, cell-based, power, layout design, layout verification ...)
Assignments:
N/A
Quiz/Test/Exam:
Final exam (70 minutes).
Reference Links
http://www.prenhall.com/rabaey
Academic Integrity
Any student who submits plagiarized work (another person's) shall receive a zero or or "F" on that homework, project or exam. Any student caught cheating on an exam shall receive an "F" in the entire course.
Attendance
Students must attend all class meetings, with the exception of an emergency or illness. Students who miss 4 or more class meetings for any reason will receive an "F" in the course.
Assignments
Assignments are due on the date assigned by the instructor.
Makeup
Late assignments, missed midterms and quizzes, etc. may be made up only with advance approval from the instructor.
Use of Library Resources in Assignments
Students will use the Library Resources at NPU as well as the Internet to research information for assignments. You may also use San Jose State's Library. The NPU Library has a SJ State Library card. Specific assignments may require students to review technical journals, magazines, textbooks, and reference books located in the NPU Library.
Guidance and Direction to the Students
The instructor and LA/TA (if applicable) are available to assist the students with the class materials and assignments.
Resources
Journal articles, reprints from reference publications, audio-visual, handouts, and other technical material developed by the instructor will be used to supplement the textbooks.
Notes
N/A
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