EE510
Northwestern Polytechnic University
Course Syllabus
LOGIC SYNTHESIS (EE510)
2007 Summer (05/02/2007 updated)
Course Description
  This is the second of the series – EE461, EE510, EE512 – for logic design implementation. This course covers both the algorithmic aspect and the practical application aspect of logic synthesis. The focus is on the use and applications of Verilog HDL in logic synthesis with high-technology industry EDA tools. The course intends to develop the students’ abilities to execute large and complicated digital design using behavioral Verilog modeling and logic synthesis. Topics include Verilog HDL constructs for logic synthesis, resource sharing, Verilog HDL coding style for synthesis, special case handling, synthesizable Verilog HDL for commonly used logic building blocks, generic module generation, notation and basic concepts in logic synthesis, two-level logic optimization, Heuristic minimization of two-level logic, binary decision diagram (BDD) and related topics, and multi-level synthesis. Cadence Verilog-XL, Mentor Leonardo for HDL Synthesis, and Synopsys Design Compiler are used for all assigned homework and projects.
 
Prerequisites
  EE461.
 
Instructor Information
  Name: Mr. Yingli Ren
Email: ren_yingli@yahoo.com
 
Instruction Methods
  Lecture notes are posted on the NPU internet. 75% of a class period is allocated to lectures while the remaining time will be spent on tools tutorials and hands-on labs.
 
Teaching Strategies
  Knowledge reinforcement; coding practice.
 
Course Information
  units: 3 units/15 weeks

Hours:

 3 hour lecture/week
  Time: Tuesdays, 6:50 P.M. - 9:40 P.M.
 
Textbook Information
  Title: Instructor's notes
Author: N/A
ISBN: N/A
publisher: N/A
Notes: Students are not allowed to use previous edition textbook.
 
Reference book Information
  Title: Logic Synthesis, By Srinivas Devadas, Abhijit Ghosh, and Kurt Keutzer
ISBN: 0070165009, Publisher: McGraw-Hill,1994
  Title: Synthesis and Optimization of digital circuits, By Giovanni De Micheli
ISBN: 0070163332, Publisher: McGraw-Hill, 1994
 
Course Objectives
Prerequisite: EE461 or HDL(Verilog or VHDL) based hardware design knowledge or experience using EDA tools such as Cadence and Synopsys.
 
Grading Policy
Lecture percentage: 100 % 
Homework Midterm Final Project Presentation Participation Quizzes Others
20% 30% 30% 0% 0% 10% 10% 0%
 
Weekly Activities:
1 Objectives: Overview:
1. Course Introduction.
2. Overview on language based hardware implmentation.
3. Overview of logic optimization.
4. Setup class mailing list.
Instructive Coverage & Activities: Overview of course scope, language based hardware design, tools used and NPU design environment.
Assignments: 1. Download course material.
2. Browse class notes.
2 Objectives: 1. Review Verilog HDL.
2. Cover Verilog synthesizable sub-set for HDL synthesis.
Instructive Coverage & Activities: 1. Categorize Verilog HDL constructs into the following
-- synthesizable
-- non-synthesizable
-- Ignored by synthesis
2. Go over the synthesizable subset to see how some of the constructs are synthesized into hardware.
Assignments: 1. Get to know the Unix environment & NPU tools environment.
2. Refamiliarize with a Unix Verilog simulator such as Verilog XL or VCS.
3 Objectives: Special case handling for Verilog HDL synthesis.
Instructive Coverage & Activities: 1. Specail case handling for Verilog HDL synthesis.
2. Go over tutorial on how to use Synopsys Design Compiler.
Assignments: HW#1: Design & synthesis of a frequency divider.
4 Objectives: Resource Sharing at Verilog HDL level for synthesis.
Instructive Coverage & Activities: 1. Resource sharing concepts & restrictions.
2. Coding style that facilitates resource sharing during Verilog HDL coding.
3. Tutorial on how to control resource sharing using Design compiler.
Assignments: HW#2: Implementing a signed multiplier using Verilog HDL.
5 Objectives: Verilog HDL coding style.
Instructive Coverage & Activities: Good Verilog HDL design practices including:
1. Design partitioning.
2. Naming convention.
3. Ways to reduce simulation & synthesis mis-matches.
Assignments: HW#3: Synthesis tool effective comparison.
Quiz/Test/Exam: Quiz #1: Verilog HDL for synthesis.
6 Objectives: Retiming in hardware design.
Instructive Coverage & Activities: 1. Retiming concepts.
2. Setting constraints under Synopsys Design Compiler for synthesis.
Assignments: HW#4: Resource Sharing practice using Synopsys Design Compiler.
7 Objectives: Verilog HDL for commonly use logic building blocks & module generation.
Instructive Coverage & Activities: 1. Verilog HDL coding for commonly used logic building blocks for synthesis.
2. Module generation concepts & its applications.
3. Review for mid-term.
Assignments: Review and prepare for Midterm exam.
8 Objectives: Midterm & introduction to the second half of the course.
Instructive Coverage & Activities: 1. Introduction to the second half of the course.
2. Midterm exam.
Assignments: HW#5: Retiming homework.
9 Objectives: Behavior level modeling & introduction to notations & basic concepts in logic synthesis.
Instructive Coverage & Activities: 1. Behavior level modeling & comparison to RTL modeling.
2. Basic notations & concpets in Logic minimization.
Assignments: HW#6: on-set, off-set & other basic operations.
10 Objectives: Two level logic minimization.
Instructive Coverage & Activities: 1. Algebraic mehtods.
2. K-map method.
3. Q-M method.
4. Iterative consensus method.
Assignments: Review course material so far. No assigned HW.
11 Objectives: Heuristic minimization of two level logic.
Instructive Coverage & Activities: 1. Local Search.
2. Expand/Reduce.
3. Heuristic minimization of two level logic.
Assignments: HW#7: Implicant & Q-M method.
Quiz/Test/Exam: Quiz #2 on basic concepts & two level logic minimization.
12 Objectives: Binary decision diagram (BDD) and related topics.
Instructive Coverage & Activities: 1. BDD overview.
2. BDD, OBDD & ROBDD.
3. BDD applications.
Assignments: HW#8 on BDD applications.
13 Objectives: Multiple level logic synthesis.
Instructive Coverage & Activities: 1. Summary of two level logic minimization & introduction to multiple level logic network.
2. Procedures in multiple logic minimization.
3. Division algorithms: Algebraic & Boolean Division.
Assignments: HW#9 Performing multiple level logic minimization either manually or using a commercial tool.
14 Objectives: Kernel, Co-Kernel & Rule based logic minimization.
Instructive Coverage & Activities: 1. Kernel & Co-Kernel.
2. Rule based logic minimization.
3. Review for final.
Assignments: HW#10: Boolean & algebraic divisions.
15 Objectives: Review and Final Exam.
Instructive Coverage & Activities: 1. Course summary.
2. Final Exam.
Assignments: All course related work are due at beginning of the class.
Reference Links
  http://www.verilog.com
 
Academic Integrity
  Any student who submits plagiarized work (another person's) shall receive a zero or or "F" on that homework, project or exam. Any student caught cheating on an exam shall receive an "F" in the entire course.
 
Attendance
  Students must attend all class meetings, with the exception of an emergency or illness. Students  who miss 4 or more class meetings for any reason will receive an "F" in the course.
 
Assignments
  Assignments are due on the date assigned by the instructor.
 
Makeup
  Late assignments, missed midterms and quizzes, etc. may be made up only with advance approval from the instructor.
 
Use of Library Resources in Assignments
  Students will use the Library Resources at NPU as well as the Internet to research information for assignments. You may also use San Jose State's Library. The NPU Library has a SJ State Library card. Specific assignments may require students to review technical journals, magazines, textbooks, and reference books located in the NPU Library.
 
Guidance and Direction to the Students
  The instructor and LA/TA (if applicable) are available to assist the students with the class materials and assignments.
 
Resources
  Journal articles, reprints from reference publications, audio-visual, handouts, and other technical material developed by the instructor will be used to supplement the textbooks.
 
Notes
  N/A
 
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