EE512

Northwestern Polytechnic University
Course Syllabus
Application Specific Integrated Circuit Design (ASIC) (EE512)
2007 Summer (05/02/2007 updated)

Course Description

In connection with EE461 and EE510, this course is designed for students who intend to become logic designers using HDL based design methodologies. Topics include ASIC/CPLD/FPGA Library modeling, Cell characterization, static timing analysis, place and route algorithms, design for testability, fault modeling, industry standard formats for design information interchange, and a survey of the most popular EDA tools. Industry grade design tools such as Synopsys Design Compiler, Cadence Verilog-XL, Synopsys DesignTime (under dc_shell), Synopsys Prime Time, Cadence Silicon Ensemble, Mentor Calibre LVS/DRC, and Synplicity Synplify are used for homework assignments and projects.

Prerequisites
	EE510

Instructor's Information
	Name:	Mr. Ren, Yingli
	Email:	ren_yingli@yahoo.com
Instruction Methods
	Students who registered for the class will receive all the class notes via email by the end of the second week. 75% of a class period is allocated to lectures while the remaining time will be spent on tools tutorials and hands-on labs.
Teaching Strategies
	Expanding HDL based hardware design knownledge & practice on leading edge hardware design tools.

Course Information
	Units:	3 units/15 weeks	Hours:	3-hour lecture/week
	Time:	Tuesday, 6:50 P.M. - 9:40 P.M.

Textbook
	Title:	Class notes provided by Instructor
	By:	Instructor
	ISBN:	N/A
	Published By:	N/A

Reference Books
	1.	Application Specific Integrated Circuit by Michael Smith, ISBN: 0201500221 Publisher: Addison-Wesley
	2.	HDL Chip Design by Douglas J. Smith, ISBN: 0965193438 Publisher: Doone Publications

Course Objectives
	Prerequisite: EE461 or HDL(Verilog or VHDL) based hardware design knowledge or experience using EDA tools such as Cadence and Synopsys. EE510 (Logic Synthesis) is recommended.

Grading Policy

Part I: Lecture 100%

Homework Midterm Final Project Presentation Participation Quizzes Other

20% 30% 30% 0% 0% 0% 0% 10%

A+ = 98-100 A = 92-97.9 A- = 90-91.9

B+ = 88-89.9 B = 82-87.9 B- = 80-81.9

C+ = 78-79.9 C = 72-77.9 C- = 70-71.9

D+ = 68-69.9 D = 62-67.9 D- = 60-61.9

F = 59 and below

Weekly Activities:

Week

Topics

1

Objectives: Introduction & course overview. Instruction on how to download course material from npu network.
Instructive Coverage & Activities: ASIC Design Overview & History. Introduction to SOC design concepts.
Assignments:
1. Browse course material.
2. Obtain Unix account & Unix skills

2

Objectives: Brief review of HDL for synthesis & synthesis algorithms.
Instructive Coverage & Activities: Design flow coverage & tools demo.
Assignments: Practice Tools Used for the course.

3

Objectives: ASIC technology library development & design techniques
Instructive Coverage & Activities:
1. ASIC technology library development
2. Delay modeling
Assignments: HW#1: Synthesizing different types designs using different technology library

4

Objectives: Boolean Optimization under Design Compiler
Instructive Coverage & Activities:
1. Boolean Optimization under Design Compiler
2. Synthesizing hierarchical designs using Design compiler.
Assignments: HW#2: Design & Synthesis of a serial controller

5

Objectives: Static Timing Analysis I/II
Instructive Coverage & Activities: Static Timing Analysis I/II
Assignments: HW#3: Manual Static timing analysis on a circuit with feedback oops.

6

Objectives: Writing Synthesis scripts for design compiler & Generating constrains for synthesis and timing analysis
Instructive Coverage & Activities: Writing Synthesis scripts for design compiler & Generating constrains for synthesis and timing analysis
Assignments: HW#4: Basic Design for Test (DFT) techniques

7

Objectives: Clock structure & clock tree synthesis and synthesis scripting
Instructive Coverage & Activities:
1. Clock structure & clock tree synthesis
2. Creating synthesis scripts
Assignments: HW#5: Create a large sequential circuit using Mux based scan methodology.

8

Objectives: Review topics so far & Midterm Exam
Instructive Coverage & Activities:
1. Review topics covered in midterm.
2. Midterm Exam
Assignments: Reading on DFT paper

9

Objectives: Design for Test (DFT) concepts & algorithms
Instructive Coverage & Activities: Design for Test (DFT) concepts & algorithms
Assignments: HW#6: Manual (Or use tool) static timing analysis on a sequential circuit

10

Objectives: Built-in-Self Test (BIST) concepts & techniques
Instructive Coverage & Activities: Built-in-Self Test (BIST) concepts & techniques
Assignments: HW#7: Static timing analysis with multiple clocks & multiple phases.

11

Objectives: Fundamentals of SPICE Simulation
Instructive Coverage & Activities: Fundamentals of SPICE Simulation
Assignments: HW#8: Combinational divider generation & synthesis of highly hierarchical modules.

12

Objectives: Physical design algorithms
Instructive Coverage & Activities: Physical design algorithms, Placement & routing using Cadence Silicon Ensemble
Assignments: HW#9: A more complex design: create building blocks

13

Objectives: Physical Verification: LVS/DRC
Instructive Coverage & Activities: Physical Verification using Mentor Calibre tools
Assignments: HW#10: A more complex design: finish the design using the building blocks created from homework #9

14

Objectives: Review
Instructive Coverage & Activities: Review for final & Question & answer on course material and homework.
Assignments: Review course material & prepare for final

15

Objectives: Wrapping up open issues & Final Exam
Instructive Coverage & Activities: List further study options on the topic & related courses. Final Exam
Assignments: Last day to turn in any course related work.

Links

http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/ASICs.htm

Academic Integrity
	Any student who submits plagiarized work (another person's) shall receive a zero or or "F" on that homework, project or exam. Any student caught cheating on an exam shall receive an "F" in the entire course.

Attendance
	Students must attend all class meetings, with the exception of an emergency or illness. Students miss 4 or more class meetings for any reason will receive an "F" from the course.

Assignments
	Assignments are due on the date assigned by the instructor.

Makeup
	Late assignments, missed midterms and quizzes, etc. may be made up only with advance approval from the instructor.

Use of Library Resources in Assignments
	Students will use the Library Resources at NPU as well as the Internet to research information for assignments. You may also use San Jose State's Library. The NPU Library has a SJ State Library card. Specific assignments may require students to review technical journals, magazines, textbooks, and reference books located in the NPU Library.

Guidance and Direction to the Students
	The instructor and LA/TA (if applicable) are available to assist the students with the class materials and assignments.

Resources
	Journal articles, reprints from reference publications, audio-visual, handouts, and other technical material developed by the instructor will be used to supplement the textbooks.