EE514
Northwestern Polytechnic University
Course Syllabus
PHYSICAL SYNTHESIS AND ADVANCED P & R (EE514)
2007 Summer (05/02/2007 updated)
Course Description
This course is designed to further investigate ASIC front-to-back design automation. The course aims to develop the students’ design ability in ASIC by using state-of-the-art EDA backend design tools and methodology (such as Cadence SE-PKS). It also introduces concepts in advanced industrial deep submicro backend design. Topics include library review, floor planning in SE, physical synthesis, CTPKS, timing closure, RCextraction, back annotated from back to front, non-default routing rule implementation, double-cut-via implementation for 0.13u and below technology, shielding, and route. Hands-on practices are required.
Prerequisites
EE508 or instructor's consent.
Instructor Information
Name:
Mr. Yihmin Liou
Email:
yihmin_liou@yahoo.com
Instruction Methods
Lecture, demos, discussions, in-class exercises, tests.
Teaching Strategies
Knowledge repetition and reinforcement - topic review, topic homework assignment (fundamental material), literature reviews and in-class presentations (broad knowledge), and hand-on design project (application and practical material).
Course Information
units:
3 units/15 weeks
Hours:
3 hour lecture/week
Time:
Thursdays, 6:50 P.M. - 9:40 P.M.
Textbook Information
Title:
Instructor's notes
Author:
N/A
ISBN:
N/A
publisher:
N/A
Notes:
Students are
not
allowed to use previous edition textbook.
Reference book Information
Title:
Appilcation Specific Integrated Circuits, By: Michael John Sebastian Smith
ISBN:
0201500221, Published by: Addison-Wesley, 1997
Course Objectives
Students will gain advanced knowledge of ASIC backend design skill and become advanced designers.
Grading Policy
Lecture percentage: 100 %
Homework
Midterm
Final
Project
Presentation
Participation
Quizzes
Others
0%
40%
20%
0%
20%
10%
0%
10%
Weekly Activities:
1
Objectives:
Week 1 and Week 2 will be covering wireload model flow, physical synthsis flow and soc prototyping flow.
Instructive Coverage & Activities:
I will be using 2 hours for lecturing and one hour for the lab. I will be using First Encounter, the Cadence tool for the lab. we will be covering wireload model flow, physical synthsis flow and soc prototyping flow and we will be do lab to each of sub topics.
Assignments:
There will be a check in and check out in the lab.
2
Objectives:
Week 1 and Week 2 will be covering wireload model flow, physical synthsis flow and soc prototyping flow.
Instructive Coverage & Activities:
I will be using 2 hours for lecturing and one hour for the lab. I will be using First Encounter, the Cadence tool for the lab. we will be covering wireload model flow, physical synthsis flow and soc prototyping flow and we will be do lab to each of sub topics.
Assignments:
There will be a check in and check out in the lab.
3
Objectives:
Silicon virtual prototyping is the topic for Week 3 and Week 4.
Instructive Coverage & Activities:
I will be covering silicon prototyping flow in soc design. usually this is for miliion gate hier. design. I will go over the concept, the flow, the EDA tools, the design and the applications. there will be a lab to go with it.
Assignments:
There will a lab for this topic.
4
Objectives:
Silicon virtual prototyping is the topic for Week 3 and Week 4.
Instructive Coverage & Activities:
I will be covering silicon prototyping flow in soc design. usually this is for miliion gate hier. design. I will be go over the concept, the flow, the EDA tools, the design and the applications. There will be a lab to go with it.
Assignments:
There will a lab for this topic.
5
Objectives:
Week 5 and Week 6 will be covering partition and hier. Design in the soc design flow.
Instructive Coverage & Activities:
I will be going over the partition concept, theory, why doing this, on what applicaiton, what is the benefit, how much extra needed, what is the trade off..etc.
Assignments:
There will be a lab for this topic.
Quiz/Test/Exam:
Take home midterm 1.
6
Objectives:
Week 5 and week 6 will be covering partition and hier. Design in the soc design flow.
Instructive Coverage & Activities:
I will be going over the partition concept, theory, why doing this, on what applicaiton, what is the benefit, how much extra needed, what is the trade off... etc.
Assignments:
There will be a lab for this topic.
7
Objectives:
Week 7 and Week 8 we will be covering the sign off engines which are signal integrity.
Instructive Coverage & Activities:
SI (signal Integrity) is very import in deep sub micro ic design espcially below 0.13u technology. in this section, I will be covering why do design need it, how to prevent it from happening, how to implement it... etc.
Assignments:
There will be a lab for this topic.
8
Objectives:
Week 7 and Week 8 we will be covering the sign off engines which are signal integrity.
Instructive Coverage & Activities:
SI (signal Integrity) is very import in deep sub micro ic design espcially below 0.13u technology. in this section, I will be covering why do design need it, how to prevent it from happening, how to implement it... etc.
Assignments:
There will be a lab for this topic.
9
Objectives:
Week 9 and Week 10, we will be talking about congestion analysis, power planning, IR drop, power analysis.
Instructive Coverage & Activities:
This topic for week 9 and week 10 is considered advance design technique in physical design. we will be looking into close on congestion in routing, how to fix them, how to prevent from happening. we will be looking into power planning, verify the power structure... etc.
Assignments:
There will be a lab for this topic.
Quiz/Test/Exam:
Take home midterm 2.
10
Objectives:
Week 9 and Week 10, we will be talking about congestion analysis, power planning, IR drop, power analysis.
Instructive Coverage & Activities:
This topic for Week 9 and Week 10 is considered advanced design technique in physical design. We will be looking into close on congestion in routing, how to fix them, how to prevent from happening. We will be looking into power planning, verify the power structure... etc.
Assignments:
There will be a lab for this topic.
11
Objectives:
Week 11 and Week 12 will be covering ipo and physical synthesis.
Instructive Coverage & Activities:
We will be taking a look at PKS(physical Knoweldegeable Synthesis). It is a front end optimaization tool. PKS is able to re-syn the design, does ipo, also does backend implementation such as clock tree, and global route. We will be using First Encounter to do netlist eco.
Assignments:
There will be a lab for pks and FE(first encounter)ipo.
12
Objectives:
Week 11 and Week 12 will be covering ipo and physical synthesis.
Instructive Coverage & Activities:
We will be taking a look at PKS(physical Knoweldegeable Synthesis). It is a front end optimaization tool. PKS is able to re-syn the design, does ipo, also does backend implementation such as clock tree, and global route. We will be using First Encounter to do netlist eco.
Assignments:
There will be a lab for pks and FE (first encounter) ipo.
13
Objectives:
Week 13 and Week 14 will be covering flip chip design.
Instructive Coverage & Activities:
I will be covering flip chip design and why need it. How to implement it.
Assignments:
There will be a lab for this topic.
Quiz/Test/Exam:
Take home midterm 3.
14
Objectives:
Week 13 and Week 14 will be covering flip chip design.
Instructive Coverage & Activities:
I will covering flip chip design and why we need it. How to implement it?
Assignments:
There will be a lab for this topic.
15
Objectives:
Week 15 is the for clock tree synthesis.
Instructive Coverage & Activities:
I will be covering clock tree. the concept of it. how FE build the clock tree. also cover high fan out nets such as re-set... etc.
Assignments:
There will be a lab for clock tree.
Quiz/Test/Exam:
Final project presentation.
Reference Links
http://www.cadence.com/products/digital_ic/physical_synthesis_dt.aspx
Academic Integrity
Any student who submits plagiarized work (another person's) shall receive a zero or or "F" on that homework, project or exam. Any student caught cheating on an exam shall receive an "F" in the entire course.
Attendance
Students must attend all class meetings, with the exception of an emergency or illness. Students who miss 4 or more class meetings for any reason will receive an "F" in the course.
Assignments
Assignments are due on the date assigned by the instructor.
Makeup
Late assignments, missed midterms and quizzes, etc. may be made up only with advance approval from the instructor.
Use of Library Resources in Assignments
Students will use the Library Resources at NPU as well as the Internet to research information for assignments. You may also use San Jose State's Library. The NPU Library has a SJ State Library card. Specific assignments may require students to review technical journals, magazines, textbooks, and reference books located in the NPU Library.
Guidance and Direction to the Students
The instructor and LA/TA (if applicable) are available to assist the students with the class materials and assignments.
Resources
Journal articles, reprints from reference publications, audio-visual, handouts, and other technical material developed by the instructor will be used to supplement the textbooks.
Notes
This class will have three take home exams, 20% for each. Lab activities will be 10%.
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