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Northwestern Polytechnic University (NPU) has been a member of the Cadence University Program since 1997. Cadence Electronic Design Automation (EDA) tools have been used extensively by the NPU engineering faculty and students from teaching and learning purposes, particularly in VLSI, Logic Design, ASIC/FPGA design courses as well as in various research projects. Tools such as Verilog-XL simulator, Silicon Ensemble and Virtuoso?layout editor are among the most popular tools used. The Cadence EDA tools are installed on the NPU Unix network system with floating licenses. Students access these tools either directly on the Sun workstations or through the Windows Based PCs with X-windows servers in the classrooms, EE laboratories, and the engineering library.

To better prepare students for future job opportunities in the high-tech industry, the electrical engineering department at NPU has successfully integrated the EDA tools, such as those from Cadence Design Systems, into the engineering curriculum. All classrooms for EE instructions are equipped with computers having access to the full suite of EDA tools at NPU.

The following is a partial list of courses that utilize Cadence Tools:

EE461 Verilog HDL & Digital Design
EE505 VLSI Design I: Rules & Methodologies
EE506 VLSI Design II: Standard Cell/Datapath
EE508 VLSI Design III: Place & Route
EE510 Logic Synthesis
EE512 ASIC Design

The following is a partial list of Cadence Tools tutorial developed by the EE instructors at NPU:

Digital Logic Simulation using Cadence Verilog-XL at NPU Electronics Lab (http://www.npu.edu/cadence/ee461/useunix.doc)
Logic Synthesis using Cadence Ambit Synthesis tool at NPU Electronics Lab (http://www.npu.edu/cadence/ee510/ambit.ppt)
ASIC Placement & Routing using Cadence Silicon Ensemble (http://www.npu.edu/cadence/ee512/notes/se.ppt)

Cadence University Program Administrators at NPU:

Administrative Staff: Dr. Bill Wu (wjw@npu.edu)

IT & Systems: David Lee (davidlee@npu.edu)

Technical Advisor: Yingli Ren (renyl@npu.edu)

Disclaimer: Information is provided as is without any warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, authorship, or otherwise.

Last Update: May 2nd, 2007

Cadence is a registered trademark of Cadence Design Systems, Inc.

2655 Seely Avenue, San Jose, CA 95134


		Cadence University Program at Northwestern Polytechnic University
		Northwestern Polytechnic University (NPU) has been a member of the Cadence University Program since 1997. Cadence Electronic Design Automation (EDA) tools have been used extensively by the NPU engineering faculty and students from teaching and learning purposes, particularly in VLSI, Logic Design, ASIC/FPGA design courses as well as in various research projects. Tools such as Verilog-XL simulator, Silicon Ensemble and Virtuoso?layout editor are among the most popular tools used. The Cadence EDA tools are installed on the NPU Unix network system with floating licenses. Students access these tools either directly on the Sun workstations or through the Windows Based PCs with X-windows servers in the classrooms, EE laboratories, and the engineering library. To better prepare students for future job opportunities in the high-tech industry, the electrical engineering department at NPU has successfully integrated the EDA tools, such as those from Cadence Design Systems, into the engineering curriculum. All classrooms for EE instructions are equipped with computers having access to the full suite of EDA tools at NPU. The following is a partial list of courses that utilize Cadence Tools: EE461 Verilog HDL & Digital Design EE505 VLSI Design I: Rules & Methodologies EE506 VLSI Design II: Standard Cell/Datapath EE508 VLSI Design III: Place & Route EE510 Logic Synthesis EE512 ASIC Design The following is a partial list of Cadence Tools tutorial developed by the EE instructors at NPU: Digital Logic Simulation using Cadence Verilog-XL at NPU Electronics Lab (http://www.npu.edu/cadence/ee461/useunix.doc) Logic Synthesis using Cadence Ambit Synthesis tool at NPU Electronics Lab (http://www.npu.edu/cadence/ee510/ambit.ppt) ASIC Placement & Routing using Cadence Silicon Ensemble (http://www.npu.edu/cadence/ee512/notes/se.ppt) Cadence University Program Administrators at NPU: Administrative Staff: Dr. Bill Wu (wjw@npu.edu) IT & Systems: David Lee (davidlee@npu.edu) Technical Advisor: Yingli Ren (renyl@npu.edu) Disclaimer: Information is provided as is without any warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, authorship, or otherwise. Last Update: May 2nd, 2007 Cadence is a registered trademark of Cadence Design Systems, Inc. 2655 Seely Avenue, San Jose, CA 95134