Cadence University Program at Northwestern Polytechnic University
Northwestern Polytechnic University (NPU) has been a member of the Cadence University Program since 1997. Cadence Electronic Design Automation (EDA) tools have been used extensively by the NPU engineering faculty and students for teaching and learning purposes, particularly in VLSI, Logic Design, Logic Synthesis, ASIC/FPGA design courses as well as in various research and student capstone projects. Tools such as Verilog XL simulator, SOC Encounter, Spectre Circuit simulator and Virtuoso layout editor are among the most popular tools used. The Cadence EDA tools are installed on the NPU Unix network system with floating licenses. Students access these tools either directly on the Sun or Linux workstations or through Windows Based PCs with X-windows servers in the classrooms, Engineering laboratories, and libraries.
To better prepare students for future job opportunities in the high-tech industry, the electrical engineering department at NPU has successfully integrated many Electronic Design Automation tools, such as those from Cadence Design Systems, into the engineering curriculum.
The following is a partial list of courses that utilize Cadence Tools:
- EE461 Verilog HDL & Digital Design
- EE505 Advanced Digital IC Design
- EE508 VLSI Design - Place & Route
- EE511 Advanced Analog IC Design
- EE512 Application Specific Integrated Circuit (ASIC) Design
- EE520 Advanced FPGA Design and Implementation
- EE595 Electrical Engineering Capstone
The custom IC design courses at NPU utilize Virtuoso schematic, Virtuoso layout and Spectre circuit simulator from Cadence Custom IC and Verification bundles.
The Semi-custom IC (ASIC) design courses utilize Verilog XL, SoC Encounter and RTL Compiler from Cadence Digital IC and Verification tool bundles.
Cadence University Program Administrators at NPU:
Administrative Staff: Elton Li(firstname.lastname@example.org)
IT & Systems: Chris Zhang, Elton Li(email@example.com)
Technical Advisor: Dr. Yingli Ren (firstname.lastname@example.org)
Disclaimer: Information is provided as is without any warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, authorship, or otherwise.
Last Update: May 11, 2016
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